Page Table

Tags

comp-arch

Is a translation table between virtual memory pages and physical frames.

For example page 1 might point to frame 45, page 2 to frame 30, etc. At any time a other or in-between frames may be assigned to another process or used internally by the OS.

Note: The page table isn't limited to just storing address translations. It can also remember properties about the page such as: is it read-only?

Size Issues on 64-bit Machines

On a 64-bit machine with a 4-bit block size we have an effective maximum number of blocks as \( 2^{52} \) (see paging for this calculation), meaning to our page table will end up with \( 2^{52} \) entries. This results in a possible page-table size of \( 2^{55} \) bytes (or 4 petabytes).

Multi-Level Page Tables

Is an approach to building page-tables where each address contains a reference to a sub-page table that'll direct to the actual page-table which will direct to the physical frame. In practice a mult-level page table can have as many sub-page tables nested as you require.

The main disadvantage to multi-level page tables is each nested sub-table is another layer of indirection that requires more memory accesses to resolve. This is one of the main reasons most modern MMUs come with a TLB.