Endianness

Tags

comp-arch

Refers to the order in which a sequence of bits is translated into memory. In general this just means which bit of a sequence stores the most significant bit (largest value).

In general a computers CPU will work equally well regardless of the choice in endianness because the hardware will consistently use the same endianness. This only becomes an issue when moving data external to the computer such as when transferring between different computers or inspecting the internal computer bytes from a memory dump and expecting a given endianness. You can convert between network and host byte orders by using ntohs and ntohl.

Big Endian

An endian-scheme which stores the most-significant bit at the smallest memory address and then pushes subsequent bits to larger memory addresses.

This essentially means that you read memory from right-to-left. For example an 8-bit value with zeroes in all but the:

• left-most column is a 1, and
• In the right-most column is a 128.

This scheme is dominant in the IP suite, where it is commonly referred to as Internet Order. Why? Because RFC1700 standardised on it and some really smart people plead for it.

Little Endian

An endian-scheme which stores the least-significant bit at the smallest memory address.

This essentially means that you read memory from left-to-right. For example an 8-bit value with zeroes in all but the:

• Left most column is a 128, and
• In the right-most column is a 1.

This scheme is the most common ordering for processor architectures and their associated memory.

Bi-Endianness

An endian-scheme supports switchable endianness.

On data/instruction fetches or stores you can specify which endianness you want to work with.